Test MP+dmb.sy+ctrl-addr-ctrl-addr-[fr-rf]

AArch64 MP+dmb.sy+ctrl-addr-ctrl-addr-[fr-rf]
"DMB.SYdWW Rfe DpCtrldR DpAddrdR DpCtrldR DpAddrdR FrLeave RfBack Fre"
Cycle=Rfe DpCtrldR DpAddrdR DpCtrldR DpAddrdR FrLeave RfBack Fre DMB.SYdWW
Relax=
Safe=Rfe Fre DMB.SYdWW DpAddrdR DpCtrldR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpCtrldR DpAddrdR DpCtrldR DpAddrdR FrLeave RfBack Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X3=z; 1:X6=a; 1:X8=b; 1:X11=x;
2:X1=x;
}
 P0          | P1                    | P2          ;
 MOV W0,#2   | LDR W0,[X1]           | MOV W0,#1   ;
 STR W0,[X1] | CBNZ W0,LC00          | STR W0,[X1] ;
 DMB SY      | LC00:                 |             ;
 MOV W2,#1   | LDR W2,[X3]           |             ;
 STR W2,[X3] | EOR W4,W2,W2          |             ;
             | LDR W5,[X6,W4,SXTW]   |             ;
             | CBNZ W5,LC01          |             ;
             | LC01:                 |             ;
             | LDR W7,[X8]           |             ;
             | EOR W9,W7,W7          |             ;
             | LDR W10,[X11,W9,SXTW] |             ;
             | LDR W12,[X11]         |             ;
Observed
    y=1; x=1; 1:X12=0; 1:X10=2; 1:X0=1;
and y=1; x=1; 1:X12=0; 1:X10=1; 1:X0=1;